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november 2007 rev 2 1/24 1 m39p0r8070e2 M39P0R9070E2 256 or 512mbit (x16, mu ltiple bank, multi-level, burst) flash memory 128 mbit low power sdram, 1.8v supply, multi-chip package feature summary multi-chip package ? 1 die of 256 (16mb x 16) or 512 mbit (32mb x 16, multiple bank, multi-level, burst) flash memory ? 1 die of 128 mbit (4 banks of 2mb x16) low power synchronous dynamic ram supply voltage ?v ddf = v dds = v ddq = 1.7 to 1.95v ?v ppf = 9v for fast program electronic signature ? manufacturer code: 20h ? 256 mbit device code: 8818 ? 512 mbit device code: 8819 package ? ecopack? (rohs compliant) flash memory synchronous / asynchronous read ? synchronous burst read mode: 108mhz, 66mhz ? asynchronous page read mode ? random access: 96ns programming time ? 4.2s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 32 mbit banks (256mb devices); 64 mbit banks (512mb devices) ? four extended flash array (efa) blocks of 64 kbits dual operations ? program/erase in one bank while read in others ? no delay between read and write operations 100,000 program/erase cycles per block security ? 64-bit unique device number ? 2112-bit user programmable otp cells block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp f for block lock-down ? absolute write protection with v ppf = v ss common flash interface (cfi) lpsdram 128 mbit synchronous dynamic ram ? organized as 4 banks of 2 mwords, each 16 bits wide synchronous burst read and write ? fixed burst lengths: 1, 2, 4, 8 words or full page ? burst types: sequential and interleaved ? maximum clock frequency: 104mhz automatic and controlled precharge low power features: ? partial array self refresh (pasr) ? automatic temperature compensated self refresh (tcsr) ? driver strength (ds) ? deep power-down mode auto refresh and self refresh tfbga105 (zad) 9 x 11mm fbga www.numonyx.com
contents m39p0r8070e2, M39P0R9070E2 2/24 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 address inputs (a0-amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 lpsdram bank select address inputs (ba0-ba1) . . . . . . . . . . . . . . . . . 10 2.3 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 flash memory chip enable input (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 flash memory output enable (g f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 flash memory write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 flash memory write protect input (wp f ) . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 flash memory reset (rp f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 flash memory deep power-down (dpd f ) . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 flash memory latch enable (l f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.11 flash memory clock (k f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.12 flash memory wait (wait f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13 lpsdram chip select (e s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.14 lpsdram column address strobe (cas s ) . . . . . . . . . . . . . . . . . . . . . . 12 2.15 lpsdram row address strobe (ras s ) . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.16 lpsdram write enable (w s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.17 lpsdram clock input (k s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.18 lpsdram clock enable (ke s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.19 lpsdram lower/upper data input/output mask (ldqm s /udqm s ) . . . 13 2.20 flash memory v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.21 lpsdram v dds supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.22 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.23 flash memory v ppf program supply voltage . . . . . . . . . . . . . . . . . . . . . . 14 2.24 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
m39p0r8070e2, M39P0R9070E2 contents 3/24 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
list of tables m39p0r8070e2, M39P0R9070E2 4/24 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. tfbga105 9x11mm - 9x12 active ball array, 0. 8mm pitch, mechanical data . . . . . . . . . . 21 table 7. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m39p0r8070e2, M39P0R9070E2 list of figures 5/24 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 5. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. tfbga105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 20
summary description m39p0r8070e2, M39P0R9070E2 6/24 1 summary description the m39p0r8070e2 and M39P0R9070E2 combine two memory devices in a multi-chip package: 256-mbit (m58pr256j) or 512-mbit (m58pr512j) multiple bank flash memory 128-mbit low power synchronous dram (th e m65ka128ae) the purpose of this document is to describe how the two memory components operate with respect to each other. it should be read in conjunction with the m58prxxxj and m65ka128ae datasheets, where all specifications required to operate the flash memory and lpsdram components are fully detailed. these datasheets are available from your local numonyx distributor. recommended operating conditions do not allow more than one memory to be active at the same time. the memory is offered in a stacked tfbga105 package. it is supplied with all the bits erased (set to ?1?).
m39p0r8070e2, M39P0R9070E2 summary description 7/24 figure 1. logic diagram 1. amax is a23 in the m39p0r8070e2 and a24 in the M39P0R9070E2. ai12813 a0-amax (1) e f dq0-dq15 v ddq m39p0r8070e2 M39P0R9070E2 g f v ss 16 w f rp f wp f v ddf dpd f e s w s v ppf v dds l f k f wait f cas s ras s ba0-ba1 2 k s ke s udqm s ldqm s
summary description m39p0r8070e2, M39P0R9070E2 8/24 table 1. signal names a0-amax (1) 1. a12-a23 (in the m39p0r8070e2) or a12-a24 (in th e M39P0R9070E2) are address inputs for the flash memory component only. address inputs dq0-dq15 common data input/output v ddq common flash and lpsdram power supply for i/o buffers v ppf flash memory optional supply voltage for fast program & erase v ddf flash memory power supply v dds lpsdram power supply v ss ground nc not connected internally du do not use as internally connected flash memory e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input l f latch enable input k f burst clock wait f wait output dpd f deep power-down low power sdram e s chip enable input w s write enable input k s lpsdram clock input ke s lpsdram clock enable input cas s column address strobe input ras s row address strobe input ba0, ba1 bank select inputs udqm s upper data input/output mask ldqm s lower data input/output mask
m39p0r8070e2, M39P0R9070E2 summary description 9/24 figure 2. tfbga connections (top view through package) 1. ball a7 is nc in the m39p0r8070e2 and it is a24 in the M39P0R9070E2. 8 7 6 5 4 3 2 1 c b a22 a2 nc d e f du a4 a17 a5 a3 a1 v ss a0 v ddf nc a21 nc a8 nc a20 nc a10 nc ba0 nc ba1 nc nc k s dq2 dq11 dq9 dq1 dq12 dq7 dq6 dq5 dq3 a24/ nc (1) nc dq0 du dq15 nc a g h j k ai12814 cas s l m a18 dpd f l f udqm s v ddq a9 9 a16 a11 a15 a14 a13 dq13 dq14 du du ldqm s wait f a12 a6 a7 a19 a23 v ss v ss v dds v ss v ss v ss v dds v ddf v dds nc wp f w f nc e s ras s nc e f ke s rp f g f v ppf v ddq v ddq v ddf v ddf v ddq v ss v ss v ss k f v ss v ss v ss dq10 dq8 dq4 nc nc nc w s
signal descriptions m39p0r8070e2, M39P0R9070E2 10/24 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connect-ed to this device. 2.1 address inputs (a0-amax) amax is equal to a23 in the m39p0r8070e2 and, to a24 in the M39P0R9070E2. a0-a11 are common to the flash memory and lpsdram components. a12-amax are address inputs for the flash memory component only. in the flash memory, the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. in the lpsdram, the a0-a11 address inputs are used to select the row or column to be made active. if a row is selected, all a0-a11 address inputs are used. if a column is selected, only the nine least significant address inputs, a0-a8, are used. in this latter case, a10 determines whet her auto precharge is used. if a10 is high (set to ?1?) during read or write, the read or write operation includes an auto precharge cycle. if a10 is low (set to ?0?) during read or write, the read or write cycle does not include an auto precharge cycle. 2.2 lpsdram bank select address inputs (ba0-ba1) the ba0 and ba1 bank select address inputs are used by the lpsdram to select the bank to be made active. the lpsdram must be enabled, the row address strobe, ras s , must be low, v il , the column address strobe, cas s , and w must be high, v ih , when selecting the addresses. the address inputs are latched on the rising edge of the clock signal, k s . 2.3 data inputs/outputs (dq0-dq15) in the flash memory, the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. in the lpsdram, the data inputs/outputs are common to all memory components. they output the data stored at the selected address during a read operation, or are used to input the data during a write operation. 2.4 flash memory chip enable input (e f ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. it is not allowed to have e f and e s all at v il at the same time, only one memory component should be enabled at a time.
m39p0r8070e2, M39P0R9070E2 signal descriptions 11/24 2.5 flash memory output enable (g f ) the output enable input controls data outputs during the bus read operation of the memory. 2.6 flash memory write enable (w f ) the write enable input controls the bus write operation of the flash memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. 2.7 flash memory write protect input (wp f ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked. (see m58pr512j datasheet for details). 2.8 flash memory reset (rp f ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 (refer to the m58prxxxj data sheet, for the value of i dd2). after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to m58prxxxj datasheet). 2.9 flash memory de ep power-down (dpd f ) the deep power-down input is used to put the flash memory in deep power-down mode. when the flash memory is in standby mode and the enhanced configuration register bit ecr15 is set, asserting the deep power-down input will caus e the memory to enter the deep power-down mode. when the device is in the deep power-down mode, the memory cannot be modified and the data is protected. the polarity of the dpd f pin is determined by ecr14. the deep power-down input is active low by default.
signal descriptions m39p0r8070e2, M39P0R9070E2 12/24 2.10 flash memory latch enable (l f ) the latch enable input latches the address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. 2.11 flash memory clock (k f ) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is ignored during asynchronous read and in write operations. 2.12 flash memory wait (wait f ) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih , output enable is at v ih , or reset is at v il . it can be configured to be active during the wait cycle or one data cycle in advance. 2.13 lpsdram chip select (e s ) the chip select input e s activates the lpsdram state machine, address buffers and decoders when driven low, v il . when high, v ih , the device is not selected. 2.14 lpsdram column address strobe (cas s ) the column address strobe, cas s , is used in conjunction with address inputs a8-a0 and ba1-ba0, to select the starting column location prior to a read or write. 2.15 lpsdram row address strobe (ras s ) the row address strobe, ras s , is used in conjunction with address inputs a11-a0 and ba1-ba0, to select the starting address location prior to a read or write. 2.16 lpsdram write enable (w s ) the write enable input, w s , controls writing to the lpsdram. 2.17 lpsdram clock input (k s ) the clock signal, k s , is used to clock the read and write cycles. during normal operation, the clock enable pin, ke s , is high, v ih . the clock signal k s can be suspended to switch the device to the self refresh, power-down or deep power-down mode by driving ke s low, v il .
m39p0r8070e2, M39P0R9070E2 signal descriptions 13/24 2.18 lpsdram clock enable ( k e s ) the clock enable, ke s , pin is used to control the synchronizing of the signals with clock signal k s . if ke s is high, v ih , the next clock rising edge is valid. when ke s is low, v il , the signals are no longer clocked and data read and write cycles are extended. ke s is also involved in switching the device to the se lf-refresh, power-down and deep power-down modes. 2.19 lpsdram lower/upper data input/output mask (ldqm s /udqm s ) lower data input/output mask and upper data input/output mask pins are input signals used to mask the read or write data. the dqm latency is two clock cycles for read operations and there is no latency for write operations. 2.20 flash memory v ddf supply voltage v ddf provides the power supply to the internal core of the flash memory component. it is the main power supply for all operations (read, program and erase). 2.21 lpsdram v dds supply voltage v dds provides the power supply to the internal core of the lpsdram component. it is the main power supply for all operations (read and write). 2.22 v ddq supply voltage v ddq is common to the flash memory and lpsdram memory components. it provides the power supply to the i/o pins and enables all outputs to be powered independently of v ddf for the flash memory, or v dds for the lpsdram. v ddq can be tied to v ddf or v dds , or can use a separate supply.
signal descriptions m39p0r8070e2, M39P0R9070E2 14/24 2.23 flash memory v ppf program supply voltage v ppf is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 enables these functions (see m58prxxxj datasheet for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed. 2.24 v ss ground v ss ground is common to the lpsdram and flash memory components. it is the reference for the core supply. it must be connected to the system ground. note: each device in a system should have v ddf , v dds , v ddq and v pph decoupled with a 0.1f ceramic capacitor close to the pin (high fre quency, inherently low inductance capacitors should be as close as possible to the package). see figure 5: ac measurement load circuit the pcb track widths should be sufficient to carry the required v ppf program and erase currents.
m39p0r8070e2, M39P0R9070E2 functional description 15/24 3 functional description the lpsdram and flash memory components have separate power supplies but share the same grounds. they are distinguished by two chip enable inputs: e f for flash and e s for the lpsdram. recommended operating conditions do not allow more than one device to be active at a time. the most common example is a simultaneous read operations on the flash memory and the lpsdram which would result in a data bus contention. therefore it is recommended to put the other devices in the high impedance state when reading the selected device. figure 3. functional block diagram 1. amax is a23 in the m39p0r8070e2 and a24 in the M39P0R9070E2. dq0-dq15 v ppf a12-amax (1) wait f k f v ss l f rp f wp f 256 mbit or 512 mbit flash memory v ddf e f g f w s k s cas s ras s 128 mbit lpsdram v dds ke s udqm s ldqm s ba0-ba1 a0-a11 v ddq w f ai12815 dpd f e s
functional description m39p0r8070e2, M39P0R9070E2 16/24 table 2. bus operations operation (1) e f g f w f l f rp f wait f (2) ke s n-1 ke s ne s ras s cas s w s a10 a9, a11 a0-a8 ba0- ba1 dq15-dq0 flash memory (3) bus read v il v il v ih v il (4) v ih the sdram must be disabled. data output bus write v il v ih v il v il (4 ) v ih data input address latch v il xv ih v il v ih data output or hi-z (5) output disable v il v ih v ih xv ih hi-z any sdram operation mode is allowed. hi-z standby v ih xx xv ih hi-z hi-z reset xx x x v il hi-z hi-z deep power- down v ih xx xv ih hi-z hi-z lpsdram (3) burst read the flash memory must be disabled. v ih xv il v ih v il v ih v il v sca (6) bs (7) data output burst write v ih xv il v ih v il v il v il v sca (6) bs (7) data input self refresh v ih v il v il v il v il v ih xx? auto refresh v ih v ih v il v il v il v ih xx? power-down with precharge any flash memory operation mode is allowed. v ih v il v il v ih v ih v ih xx? v ih xxx deep power- down v ih v il v il v ih v ih v il xx? device deselect v ih xv ih xxx x x ? no operation v ih xv il v ih v ih v ih xx? 1. x = don't care, v = valid. 2. wait f signal polarity is confi gured using the set configuration register command. 3. for further details, refer to the m58prxxxj and m65ka128ae datasheets. 4. l f can be tied to v ih if the valid address has been previously latched. 5. depends on g f 6. sca = start column address. 7. bs = bank select.
m39p0r8070e2, M39P0R9070E2 maximum rating 17/24 4 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?25 85 c t j sdram operating junction temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?55 125 c v io input or output voltage ?0.5 2.3 v v ddf supply voltage ?1.0 3.0 v v dds lpsdram supply voltage ?0.5 2.3 v v ddq input/output supply voltage ?0.5 2.3 v v ppf program voltage ?1.0 11.5 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
dc and ac parameters m39p0r8070e2, M39P0R9070E2 18/24 5 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 4. ac measurement i/o waveform table 4. operating and ac measurement conditions parameter (1) 1. all voltages are referenced to v ss = 0v. flash memory lpsdram unit min max min max v ddf supply voltage 1.7 1.95 ? ? v v dds supply voltage ??1.71.95v v ddq supply voltage 1.7 1.95 1.7 1.95 v v ppf supply voltage (factory environment) 8.5 9.5 ? ? v v ppf supply voltage (application environment) ?0.4 v ddq +0.4 ? ? v ambient operating temperature ?25 85 ?25 85 c load capacitance (c l )3030pf output impedance (z 0 )50 output circuit protection resistance (r) 50 input rise and fall times 3 0.5 ns input pulse voltages 0 to v ddq ?v output timing ref. voltages 0.3v ddq 0.7v ddq v ddq /2 v ai06161 v ddq 0v v ddq /2
m39p0r8070e2, M39P0R9070E2 dc and ac parameters 19/24 figure 5. ac measurement load circuit please refer to the m65ka128ae and m58prxxxj datasheets for further dc and ac characteristic values and illustrations. table 5. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v ? 12 pf c out output capacitance v out = 0v ? 15 pf ai12818 v dd /2 out c l includes probe capacitance device under test c l r z 0
package mechanical m39p0r8070e2, M39P0R9070E2 20/24 6 package mechanical in order to meet environmental requirements, numonyx offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 6. tfbga105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline 1. drawing is not to scale. e d eb se a2 a1 a bga-z79 ddd fd d1 e1 e fe ball "a1"
m39p0r8070e2, M39P0R9070E2 package mechanical 21/24 table 6. tfbga105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.20 0.008 a2 0.80 0.031 b 0.35 0.30 0.40 0.014 0.012 0.016 d 9.00 8.90 9.10 0.354 0.350 0.358 d1 6.40 0.252 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 8.80 0.346 e 0.80 ? ? 0.031 ? ? fd 1.30 0.051 fe 1.10 0.043 se 0.40 0.016
part numbering m39p0r8070e2, M39P0R9070E2 22/24 7 part numbering note: devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 7. ordering information scheme example: m39 p 0 r 9 0 7 0 e 2 zad e device type m39 = multi-chip package (flash + lpsdram) flash 1 architecture p = multi-level, multiple bank, large buffer flash 2 architecture 0 = no die operating voltage r = v ddf = v dds = v ddq = 1.7 to 1.95v flash 1 density 8 = 256 mbits 9 = 512 mbits flash 2 density 0 = no die ram 1 density 7 = 128 mbit ram 0 density 0 = no die parameter blocks location e = even block flash memory configuration product version 2 = 90nm flash technology, 96ns speed; lpsdram package zad = stacked tfbga105 d stacked footprint. option e = ecopack? package, standard packing f = ecopack? package, tape & reel packing
m39p0r8070e2, M39P0R9070E2 revision history 23/24 8 revision history table 8. document revision history date revision changes 03-apr-2006 0.1 initial release. 14-sep-2006 1 document status prom oted from target specification to full datasheet. lpsdram power-up removed from table 2: bus operations . 30-nov-2007 2 applied numonyx branding.
m39p0r8070e2, M39P0R9070E2 24/24 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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